The contents of this answer record provide information on how distributed memory can be used to improve timing or reduce block RAM utilization in your design.
NOTE: This answer record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 series devices. Whether you are starting a new design with 7 series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
Distributed memory is a memory element that is implemented using slice logic in fabric. In projects where available block RAM blocks are completely used up, distributed memory can be used to provide additional resources for implementing RAMs and ROMs.
In addition, in circumstances where timing is critical in your design, distributed memory can be used to help make it easier to meet timing in the design. Distributed memory is implemented in slice logic, so it has the added ability to be placed close to logic in areas where timing is critical.
The LogiCORE IP Distributed Memory Generator core can be used to implement memory elements based on distributed memory in your design. For more information on this core, see the LogiCORE IP Distributed Memory Generator web page. The documentation section on the right side of the page directs you to the data sheet for this core: http://www.xilinx.com/products/intellectual-property/DIST_MEM_GEN.htm