UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - All Programmable
  2. Support
  3. AR# 46513: 7 Series FPGA Design Assistant - Designing Block RAM and FIFO structures in 7 Series FPGAs

AR# 46513

7 Series FPGA Design Assistant - Designing Block RAM and FIFO structures in 7 Series FPGAs

Description

This Answer Record provides information on how to use the block RAM and FIFO blocks in the7 Series FPGA fabric.

NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.

Solution

The built in block RAM and FIFO primitives in the 7 SeriesFPGA can be used to implement RAMs, ROMs, and FIFO blocks for a design. The block RAM and FIFO are optimized for performance and allow you to implement a RAM, ROM, or FIFO block in a design without requiring large amounts of fabric resources from slice logic.

The7 Series FPGAs Memory Resources User Guide (UG473) provides additional details on the block RAM and FIFOs. It is recommended that you read through the user guides to familiarize yourself with its use and how they can be used in your design:
http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf

In addition, the following answer records are useful in providing details on different ways to implement block RAMs and FIFO blocks in your code:
(Xilinx Answer 46515) - How to infer the use of Block RAM and FIFO primitives in your HDL code
(Xilinx Answer 46516) - Using block RAM CORE Generator and FIFO CORE Generator to setup the blocks for use in HDL code

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46516 7 Series FPGA Design Assistant - Using block RAM CORE Generator and FIFO CORE Generator to set up the blocks for use in HDL code N/A N/A
46515 7 Series FPGA Design Assistant - How to infer the use of Block RAM and FIFO primitives in your HDL code N/A N/A
46504 7 Series FPGA Design Assistant - Information about the Clocking Wizard N/A N/A
46505 7 Series FPGA Design Assistant - Details on using different clocking buffers N/A N/A
46509 7 Series FPGA Design Assistant - Utilizing distributed memory in fabric N/A N/A
46510 7 Series FPGA Design Assistant - Setting logic controls in the fabric N/A N/A
46511 7 Series FPGA Design Assistant - Using SRLs to conserve resources N/A N/A
46512 7 Series FPGA Design Assistant - Using optimization features from third-party synthesis tools N/A N/A
46489 7 Series FPGA Design Assistant - Designing for 7 series FPGAs N/A N/A
AR# 46513
Date 12/15/2012
Status Active
Type General Article
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
Page Bookmarked