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This Answer Record provides information on how to use the block RAM and FIFO blocks in the7 Series FPGA fabric.
NOTE: This Answer Record is part of the Xilinx 7 Series FPGA Solution Center (Xilinx Answer 46370). The Xilinx 7 Series FPGA Solution Center is available to address all questions related to 7 Series devices. Whether you are starting a new design with 7 Series FPGAs or troubleshooting a problem, use the 7 Series FPGA Solution Center to guide you to the right information.
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
46516 | 7 Series FPGA Design Assistant - Using block RAM CORE Generator and FIFO CORE Generator to set up the blocks for use in HDL code | N/A | N/A |
46515 | 7 Series FPGA Design Assistant - How to infer the use of Block RAM and FIFO primitives in your HDL code | N/A | N/A |
46504 | 7 Series FPGA Design Assistant - Information about the Clocking Wizard | N/A | N/A |
46505 | 7 Series FPGA Design Assistant - Details on using different clocking buffers | N/A | N/A |
46509 | 7 Series FPGA Design Assistant - Utilizing distributed memory in fabric | N/A | N/A |
46510 | 7 Series FPGA Design Assistant - Setting logic controls in the fabric | N/A | N/A |
46511 | 7 Series FPGA Design Assistant - Using SRLs to conserve resources | N/A | N/A |
46512 | 7 Series FPGA Design Assistant - Using optimization features from third-party synthesis tools | N/A | N/A |
46489 | 7 Series FPGA Design Assistant - Designing for 7 series FPGAs | N/A | N/A |
AR# 46513 | |
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Date | 12/15/2012 |
Status | Active |
Type | General Article |
Devices |
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