UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46554

Vivado Timing - write_xdc expands all_registers command

Description

I have the following constraint in my design:

set_false_path -from [get_ports tss_clk] -to [all_registers -edge_triggered]

When I issue a write_xdc for this design, it will expand all_registers so that all cells are now defined. This is very messy.

Solution

The workaround is to manually re-write the XDC file.
AR# 46554
Date Created 01/17/2013
Last Updated 08/07/2013
Status Active
Type Known Issues
Tools
  • Vivado Design Suite