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AR# 4658

A1.5/F1.5 5200 PAR - Problems with placement of TBUFs when the F5_MUX is used.

Description

KEYWORDS: PAR, TBUFs, CLB, 5200, EPIC

URGENCY: Hot

PROBLEM LONG DESCRIPTION:
PAR is not checking the validity of the placement of TBUFs when the F5_MUX is used.

When targeting a 5200 device, TBUFs must be placed so that their source is from the adjacent CLB. However, PAR places TBUFs so that they cannot be sourced from the adjacent CLB.

This problem is caused by the placement of two 5-bit functions using the F5_BUXs in the CLB along with more TBUFs than can be sourced by the CLB. When 2 F5_MUXs are placed in a CLB, this leaves only 2 possible through-routes for TBUFs that are not sourced by the F5_MUXs. However, PAR will sometimes place 3 or 4 TUBs at the CLB eventhough only 2 of them can be routed.

Solution

RESOLUTION:
The workaround to this problem is to manually check and manually re-arrange the TBUFs in the design in EPIC.

A fix for this problem will be in the M1.5i Performance Pack Update due to
begin shipping in December 1998.
AR# 4658
Date Created 08/31/2007
Last Updated 10/21/2008
Status Archive
Type General Article