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AR# 46617

MIG 7 Series - QDRII+ design missing PHASER_OUT constraints for Read Data Paths

Description

Version Found: v1.4
Version Resolved and other Known Issues: See(Xilinx Answer 45195).

Previously, in MIG 7 Series v1.2, Read Data Banks required a PHASER_OUT driven by CQ# to drive the CLKB input to the ILOGIC shown in Figure 2-30 in UG586.

Starting with MIG 7 Series v1.3, the CPT_CLK_CQ_ONLY parameter was added and set to TRUE by default, which changes the CQ/CQ# functionality so that the PHASER_OUTs are no longer needed in the Read Data Banks, and their corresponding placement constraints are now removed from the UCF.

In MIG 7 Series v1.4, there is a known issue where the PHASER_OUTs are still enabled and used regardless of what CPT_CLK_CQ_ONLY is set to, and in some cases the following error can occur:

ERROR: [Place-370] An unconstrained Phaser instance has been found. Phaser instances and their associated I/O logic must be LOC constrained to a legal site locations for placement to succeed. Check to see whether all core constraints were properly used or manually add LOC constraints for the following instance(s).
Unconstrained Phaser instance(s):
Inst 'u_qdr_a_14/u_qdr_phy_top/u_qdr_rld_mc_phy/qdr_rld_phy_4lanes_2.qdr_rld_phy_4lanes/qdr_rld_byte_lane_D.qdr_rld_byte_lane_D/PHASER_OUT_inst.phaser_out'

Solution

This is a result of the PHASER_OUTs not being constrained in the UCF.

To work around the error, the user must manually add the missing PHASER_OUT constraints into the UCF, for example:

INST "*/qdr_rld_phy_4lanes_1.qdr_rld_phy_4lanes/qdr_rld_byte_lane_D.qdr_rld_byte_lane_D/PHASER_OUT_inst.phaser_out"
LOC=PHASER_OUT_PHY_X1Y15;
INST "*/qdr_rld_phy_4lanes_1.qdr_rld_phy_4lanes/qdr_rld_byte_lane_C.qdr_rld_byte_lane_C/PHASER_OUT_inst.phaser_out"
LOC=PHASER_OUT_PHY_X1Y14;
INST "*/qdr_rld_phy_4lanes_1.qdr_rld_phy_4lanes/qdr_rld_byte_lane_B.qdr_rld_byte_lane_B/PHASER_OUT_inst.phaser_out"
LOC=PHASER_OUT_PHY_X1Y13;
INST "*/qdr_rld_phy_4lanes_1.qdr_rld_phy_4lanes/qdr_rld_byte_lane_A.qdr_rld_byte_lane_A/PHASER_OUT_inst.phaser_out"
LOC=PHASER_OUT_PHY_X1Y12;

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45195 MIG 7 Series - Release Notes and Known Issues for All ISE versions and Vivado 2012.4 and older tool versions N/A N/A
AR# 46617
Date Created 03/01/2012
Last Updated 08/27/2014
Status Active
Type Known Issues
IP
  • MIG
  • MIG 7 Series