Version Found: 1.02.a
Version Resolved and other Known Issues: See
(Xilinx Answer 44969)If a large read request is received from the AXI interface which is split into smaller memory read TLPs to be sent to the PCIe system, it is possible that a completion timeout can be triggered. This happens if the first Memory Read TLP is sent, and the following reads are stalled due to lack of credits from the link partner. The completion timeout logic starts counting based on the AXI read request instead of the individual TLP request sent to the PCIe system. In this scenario the timer may expire before the completions for all memory reads are returned, due to the subsequent reads being stalled due to lack of credits.