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AR# 46623

AXI Bridge for PCI Express - Using 128-bit Interface (x8 Gen 1 or x4 Gen 2), an array size mismatch occurrs on Completions with Data with status of Completor Abort or Unsupported Request


Version Found: 1.02.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When using the 128-bit interface (x8 Gen 1 or x4 Gen 2), an issue exists in the bridge logic causing an array size mismatch to be exposed, resulting in a simulation run time error and incorrect bits to be set in hardware. This happens only when Completion TLPswith status of either Completer Abort or Unsupported Request are received.


It is unusual to receive Completions TLPswith status other than successful completion, so the likelihood of experiencing this issue is low. This issue is fixed in v1.03a, which will be released in ISE 14.1 software.Prior to the ISE 14.1 software release, if this issue is a concern, please open a case with Xilinx support and refer to this answer record.

Revision History
03/05/2012 - Initial Release

NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

Linked Answer Records

Master Answer Records

AR# 46623
Date Created 03/02/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
  • AXI PCI Express (PCIe)