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AR# 46624 AXI Bridge for PCI Express - Using Root Port configuration a packet that does not actually target the BAR can be passed to the AXI Memory Mapped Bridge

Description

Version Found: 1.02.a
Version Resolved and other Known Issues: see (Xilinx Answer 44969)

When operating in Root Port mode, if an incoming TLP misses the BAR, it will still be passed to the AXI MM bridge. However, the bridge does not correctly identify that the TLP did not hit the BAR, and thisresults in the possibility of a corrupted read or write address on the TLP.

Solution

It is unusual to receive a TLP with an incorrect address in a real system, so the likelihood ofof experiencing this issue is low.

This issue is fixed in v1.03a which will be released in ISE 14.1 software.Prior to ISE 14.1 release, if this issue is a concern, please open a case with Xilinx support and refer to this answer record.

Revision History
03/05/2012 - Corrected link to version resolved AR.
03/05/2012 - Initial Release

NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45988 AXI Bridge for PCI Express - 1 DW Write Transactions on the AXI4 Slave interface create malformed TLPs when using a 32-bit AXI data width N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions N/A N/A

Actions

AR# 46624
Date Created 03/02/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
IP
  • AXI PCI Express (PCIe)
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