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AR# 46638

AXI Bridge for PCI Express - The bridge does not respond to memory read requests with a length of 0 when configured as x4 gen2 or x8 gen1

Description

Version Found: 1.02.a
Version Resolved and other Known Issues: See (Xilinx Answer 44969)

When the AXI Bridge for PCI Express is configured as x4 gen2 or x8 gen1, incoming memory read request TLPs will be dropped when the length field of the TLP is zero. x4 gen2 and x8 gen1 both use the 128-bit AXI data width interface, which is why this is only seen in only those configurations.

Solution

If a system issues memory read requests with a length of zero, a completion timeout will occur in the system. To work around this issue, make sure to have all requests have a payload in all memory read requests.

A fix for this issue is not yet available, but is being investigated. If this issue is a concern please open a case with Xilinx support and refer to this answer record.

Revision History

03/05/2012 - Initial Release

NOTE:The "Version Found" columnlists the version in which the problem was firstdiscovered. The problem might also exist in earlier versions, but no specific testing has been performedto verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44969 AXI Bridge for PCI Express - Release Notes and Known Issues for All Versions up to ISE 14.7 N/A N/A
AR# 46638
Date Created 03/02/2012
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • AXI PCI Express (PCIe)