We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46698

MIG v3.9 Spartan-6 FPGA MCB - wr_mask error in two 64-bit ports configuration


When using the MIG v3.9 Spartan-6 MCB core targeting VHDL, read errors may be seen on the MSB 32-bits of port1 data when using the two 64-bit port configuration.

These 32 bits cannot be masked.

This is a bug within the mcb_raw_wrapper.vhd file.

The code below is from the mcb_raw_wrapper.vhd file:

p1_c4_ena: if (C_PORT_ENABLE(1) = '1') generate

                        mig_p2_arb_en      <=      p1_arb_en ;
                        mig_p2_cmd_clk     <=      p1_cmd_clk  ;
                        mig_p2_cmd_en      <=      p1_cmd_en   ;
                        mig_p2_cmd_ra      <=      p1_cmd_ra  ;
                        mig_p2_cmd_ba      <=      p1_cmd_ba   ;
                        mig_p2_cmd_ca      <=      p1_cmd_ca  ;
                        mig_p2_cmd_instr   <=      p1_cmd_instr;
                        mig_p2_cmd_bl      <=      ((p1_cmd_instr(2) or p1_cmd_bl(5)) & p1_cmd_bl(4 downto 0))  ;                           

                         mig_p2_clk     <= p1_rd_clk;
                         mig_p3_clk     <= p1_wr_clk;
                         mig_p4_clk     <= p1_rd_clk;
                         mig_p5_clk     <= p1_wr_clk;
                         mig_p3_en      <= p1_wr_en and not p1_wr_full_i;
                         mig_p5_en      <= p1_wr_en and not p1_wr_full_i;
                         mig_p3_wr_data  <= p1_wr_data(31 downto 0);
                         mig_p3_wr_mask  <= p1_wr_mask(3 downto 0);
                         mig_p5_wr_data  <= p1_wr_data(63 downto 32);
                         mig_p5_wr_mask  <= p1_wr_mask(3 downto 0);  <------------------- bug here


Please find the above code in the mcb_raw_wrapper.vhd file and modify the last line.

The last line should be modified as follows:

                         mig_p5_wr_mask  <= p1_wr_mask(7 downto 4);

This issue is resolved in MIG v3.92 available in ISE 14.2.

Revision History:
8/26/2014 - Initial Release
AR# 46698
Date Created 03/06/2012
Last Updated 08/27/2014
Status Active
Type General Article
  • Spartan-6
  • ISE Design Suite - 13.4
  • MIG