When coding for a Spartan-6 FPGA design, you should follow the coding guidelines shown in the language templates and also follow the recommendations for coding practices discussed in the
HDL Coding Practices to Accelerate Design Performance White Paper (WP231):
http://www.xilinx.com/support/documentation/white_papers/wp231.pdf Follow the recommendations mentioned in this White Paper, so that the software tools optimally utilize the FPGA fabric. You can also refer to the following Answer Records for more information on coding methods that can help optimize performance and reduce the amount of logic used in a design:
(Xilinx Answer 46752) - Utilizing distributed memory in fabric
(Xilinx Answer 46738) - Setting logic controls in the fabric
(Xilinx Answer 46765) - Using SRLs to conserve resources
(Xilinx Answer 46766) - Using optimization features from third-party synthesis tools
In addition, the
Spartan-6 FPGA Configurable Logic Block User Guide (UG384) describes the primitives and blocksin more detail so that you have a better understanding of how the Spartan-6 FPGA fabric can work for you in a design:
http://www.xilinx.com/support/documentation/user_guides/ug384.pdf