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AR# 46748

Spartan-6 FPGA Design Assistant - How to infer the use of block RAM and FIFO primitives in your HDL code


The following Answer Record points you to information on how to infer block RAM and FIFO primitives in your HDL code.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.


Block RAMs and FIFOs can be inferredif implemented correctly in your HDL code.The XST User Guide (UG627) discusses in detail how you need to code in order to infer a block RAM or FIFO in your design:

Specifically, the "RAMs and ROMs Hardware Description Language (HDL) Coding Techniques" section provides details on how to infer RAMs and ROMs built using block RAM in your design.

In addition, theHDL Coding Practices to Accelerate Design Performance White Paper (WP231)provides additional information on coding techniques that can be used to optimize performance of Block RAM in your design.Refer tothe "Maximize Block RAM performance" section:

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44744 Spartan-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46740 Spartan-6 FPGA Design Assistant - Designing block RAM in Spartan-6 FPGAs N/A N/A
AR# 46748
Date Created 03/27/2012
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q