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AR# 46750

Spartan-6 FPGA Design Assistant - Details on using different clocking buffers

Description

The different clock buffers available in the Spartan-6 device family allowfor clock distribution on a variety of applications. This Answer Record contains information on where to find the documentation for each of the different clock buffers available in the Spartan-6 device family.

NOTE: This Answer Record is part of the XilinxSpartan-6 FPGA Solution Center (Xilinx Answer 44744).The XilinxSpartan-6 FPGASolution Center is available to address all questions related toSpartan-6 devices.Whether you are starting a new design withSpartan-6 FPGA or troubleshooting a problem, use theSpartan-6 FPGA Solution Center to guide you to the right information.

Solution

Spartan-6 contains two types of clock buffers - 1) Clock buffers for the Global Clock Network and 2) Clock buffers for the High Speed I/O Clock Network.

The following are buffersfor the Global Clock Network:

  • BUFG
  • BUFGCE
  • BUFGMUX
  • BUFH

BUFG/BUFGCE/BUFGMUX
The BUFG/BUFGCTRL/BUFGMUX are used for Global clocks that need to reach logic throughout the entire device. You canreach the BUFG buffers through aGlobal Clock pin (GCLK pin), from a the Clock Management Tile (DCM or PLL), and from local routing (which is not recommended for most situations). If you would like more information regarding how to use the BUFG buffers, you can find this informationin the Global Clocking Resources section of theSpartan-6 Clocking Resources Users Guide (UG382):
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

BUFH
The horizontal clock buffer (BUFH) allows access to one half of an HCLK row clock. The BUFH drives a single clock signal in the half of the HCLK row. The BUFH is used to clock interconnect logic, SelectIO logic, SDP48A1 tiles, or block RAM resources. The BUFH is accessed using FPGA interconnect logic or directly using any clock output from a DCM, PLL, or GTP DUALtile in the sameHCLK row.For more information on how to use the BUFH buffer, you can find this information in theGlobal Clocking Resources section of theSpartan-6 Clocking Resources Users Guide (UG382):
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

The following are buffersfor the High Speed I/OClock Network:

  • BUFIO2
  • BUFPLL
  • BUFPLL_MCB

BUFIO2
The BUFIO2 buffer has multiple functions depending on how the user sets it up. For usage with the DCM or PLL, it is part of thededicated inputrouting and deskew path used toin conjunction withtheDCM and/or PLL. TheBUFIO2 is also a dedicated buffer for high speed I/O clocks used to clock the IOSERDES.In this usage, it has the ability toprovide a divided clock and send aSERDES strobe. The BUFIO2 can only drive the I/Os in the half bank in which it is located, so be aware of placement when using it. If you would like additional information on how to use this buffer, you can find this informationin theClockingBuffers sectionof the Spartan-6 Clocking Resources Users Guide (UG382):
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

BUFPLL

The BUFPLL is intended for high speed I/O routing to generate clocks and strobe pulses for the ISERDES and OSERDES in SDR modes. The BUFPLL must be driven by the PLL directly,can only be used in SDR mode, and can connect to any I/Os in the bank in which it is located. The BUFPLL also aligns the SERDESSTROBE to the IOCLK when adivided GCLK is given as a reference, and provides a LOCK outputas an indicator of valid operation.If you would like additional information on how to use this buffer, you can find this informationin theClockingBuffers sectionof the Spartan-6 Clocking Resources Users Guide (UG382):
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf



BUFPLL_MCB

The BUFPLL_MCB is a dedicated resource for the integrated Memory Controller Block and can only be used by the Memory Interface Generator (MIG) tool. Theimplementation ofone BUFPLL_MCB in a bankactually usesthat bank's two BUFPLLs inhardware, so as a result, a BUFPLL_MCB and a BUFPLL cannot be used in the same bank. If you would like additional information on how to use this buffer, you can find this informationin theClockingBuffers sectionof the Spartan-6 Clocking Resources Users Guide (UG382):
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44744 Spartan-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46744 Spartan-6 FPGA Design Assistant - Designing clocking structures in Spartan-6 FPGAs N/A N/A
AR# 46750
Date Created 03/27/2012
Last Updated 01/31/2013
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q