AR# 46778 14.4 EDK, Zynq-7000 - How do I configure the PS DDRC?
Description
Solution
The PS DDR controller requires board measurements converted to timing parameters programmed into the design software to calibrate the memory interface. All designs that intend to use the PS DDR interface must enter these settings into tools, either by importing a design board, or by entering the values into the Training/Board Detail section of the design tools as shown below:
img-177.png
Enter the midpoint of trace lengths for the group of signals listed under Length and adjust the associated Propagation Delay if necessary. The Package Length (mils) defaults are extracted from the package delays, and can be set to 0 if the Length (mm) measurement already includes the Zynq package delay. The memory package trace lengths can also be included in the Length (mm) measurement.
For more information, see:
- the Help button in the DDR Configuration page inside of XPS.
- the "Initialization and Calibration" section of the "DDR Memory Controller" chapter of the Zynq-7000 Extensible Processing Platform Technical Reference Manual (UG585).
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 52540 | Zynq-7000 AP SoC - Frequently Asked Questions | N/A | N/A |
| 53051 | Zynq-7000 AP SoC - PS DDR Controller | N/A | N/A |
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