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AR# 46792

Spartan-6 FPGA Design Assistant - Troubleshoot common block RAM/FIFO problems


This Answer Record helps guide you to solutions to common problems with the block RAM and FIFO resources inSpartan-6FPGA designs.

NOTE:This Answer Record is part of the XilinxSpartan-6FPGA Solution Center(Xilinx Answer 44744).The XilinxSpartan-6FPGA Solution Center is available to address all questions related toSpartan-6devices. Whether you are starting a new design withSpartan-6FPGA or troubleshooting a problem, use theSpartan-6FPGA Solution Center to guide you to the right information.


Select from the followinglist of common block RAM or FIFO related problems.Each Answer Record helps guide you to a solution:
  • (Xilinx Answer 40529)Spartan-6 - 9K Block RAM Initialization Not Supported (List of Affected IP)
  • (Xilinx Answer 44192)Design Advisory for Spartan-6 FPGA Speed File - Updates for Block RAM fMAX in Lower Power -1L Devices
  • (Xilinx Answer 34533)Design Advisory for Spartan-6 FPGA Block RAM - Address Space Overlap
  • (Xilinx Answer 34541)Design Advisory for Spartan-6 FPGA Block RAM - 9K Block RAM Simple Dual Port (SDP) Data Width Restriction
  • (Xilinx Answer 34712)Design Advisory for Spartan-6 FPGA Block RAM - 9K Simple Dual Port (SDP) Block RAM Initialization Incorrect
  • (Xilinx Answer 39977)Spartan-6 Block RAM - Configuration Readback is not supported in 9K block RAM
  • (Xilinx Answer 39999)Design Advisory for Spartan-6 FPGA - 9K Block RAM Initialization Support

If you still have a problem after running through the suggestions, open up a WebCase through Xilinx Technical Support:


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44744 Spartan-6 FPGA Solution Center N/A N/A

Associated Answer Records

AR# 46792
Date Created 03/27/2012
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT