We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 46794

Spartan-6 FPGA Design Assistant - Board Level Considerations


This section of theSpartan-6FPGA Design Assistant focuses on getting started with theSpartan-6FPGA. Select from the options below to find information related to your specific question.

NOTE:This Answer Record is part of the XilinxSpartan-6FPGA Solution Center(Xilinx Answer 44744). The Xilinx Spartan-6FPGA Solution Center is available to address all questions related toSpartan-6devices.Whether you are starting a new design withSpartan-6FPGA or troubleshooting a problem, use theSpartan-6FPGA Solution Center to guide you to the right information.



For information on power estimation, optimization, and system design, see the Power Solutions page: http://www.xilinx.com/products/design_resources/power_central/


For information on configuration solutions and debugging, see (Xilinx Answer 34904)Configuration Solutions Center .

Signal Integrity

For Signal Integrity considerations and information, see the Signal Integrity page:


For packaging requirements, see the Spartan-6 FPGA Packaging and Pinout Specifications(UG385): http://www.xilinx.com/support/documentation/user_guides/ug385.pdf

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
44744 Spartan-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46764 Spartan-6 FPGA Solution Center - Design Assistant N/A N/A
AR# 46794
Date Created 03/27/2012
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q