The Zynq-7000 IBIS models are available on Xilinx.com under Device Models -> IBIS Models -> Zynq-7000 AP SoC -> Zynq-7000 IBIS Model:
http://www.xilinx.com/support/download/index.htm
The following IBIS models should be used for DDRC simulation:
Address/Clock Signals (DDR_A, DDR_CKE, DDR_BA, DDR_ODT, DDR_WE_B, DDR_CAS_B, DDR_RAS_B DDR_CS_B, DDR_CK_P, DDR_CK_P, DDR_DRST_B):
DDR3:
SSTL15_S_PSDDRDDR2:
SSTL18_I_S_PSDDRLPDDR2:
HSUL_12_DCI_S_PSDDRData Signals (DDR_DQ, DDR_DM,DDR_DQS_P, DDR_DQS_N):
SSTL15_T_DCI_F_HP_IN40_I (input) (NOTE:This input model assumes a 40Ohm DCI termination, use SSTL15_T_DCI_F_PSDDR_I for 50 Ohm DCI termination.)DDR2:
SSTL15_T_DCI_F_PSDDR_O (output)
SSTL18_II_DCI_F_PSDDR_I (input) (NOTE: This input model assumes a 50 Ohm DCI termination.)LPDDR2:
SSTL18_II_DCI_F_PSDDR_O (output)
HSUL_12_DCI_F_PSDDROther PS I/O, including MIO, should use one of the high-range (HR) based I/O models, depending on the bit field settings of the individual MIO pin MIO_PIN_xx registers: IO_Type and Speed (Slow or Fast edge rate).
HSTL_I_18_F_PSMIOFor details of how to use the IBIS models and package files, see (Xilinx Answer 21632) .
HSTL_I_18_S_PSMIO
LVCMOS18_F_8_PSMIO
LVCMOS18_S_8_PSMIO
LVCMOS25_F_8_PSMIO
LVCMOS25_S_8_PSMIO
LVCMOS33_F_8_PSMIO
LVCMOS33_S_8_PSMIO
LVTTL_F_8_PSMIO
LVTTL_S_8_PSMIO
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 52540 | Zynq-7000 AP SoC - Frequently Asked Questions | N/A | N/A |
| 53051 | Zynq-7000 AP SoC - PS DDR Controller | N/A | N/A |