AR# 46880 Zynq-7000 Example Design - Linear QSPI Performance (Max Effective Throughput)
Description
This example design shows how to achieve QSPI (in Linear Mode) Maximum Effective Throughput with a 100 MHz SPI clock.
| Implementation Details | |||
|---|---|---|---|
| Design Type | PS only | ||
| SW Type | Standalone | ||
| CPUs | Single CPU @ 720MHz | ||
| PS Features | QSPI ( in linear mode) with SPI clock @ 100MHz DMA DDR @ 533MHz | ||
| PL Cores | -- | ||
| Boards/Tools | ZC702 (modified to have MIO[8] n.c. in order to enable the qspi loopback). | ||
| Xilinx Tools Version | EDK 14.1 | ||
| Other details | -- | ||
| Files Provided | |||
| xdmaps_example_w_intr_14_2.c | Snippet of code. | ||
Block Diagram | |||
 | |||
Solution
Overview
In order to achieve Linear Mode Maximum Effective Throughput with 100 MHz SPI clock, the DMA controller has been used.
This very flexible DMA can execute a few lines of microcode in order to transfer data from the Linear QSPI to DDR.
Following is an example of microcode that moves 256 Kbytes from LQSPI to DDR:
DMAMOV CCR, SB16 SS32 DB16 DS32
DMAMOV SAR, 0xFC000000
DMAMOV DAR, 0x00300000
DMALP 256
DMALP 256
DMALD
DMAST
DMALPEND
DMALPEND
DMAEND
The QSPI is set to operate in Linear Mode: single SPI flash memory, Fast read quad I/O (LQSPI_CFG = 0x82FF04EB ).
SPI reference clock: 200 MHz
SPI clock: 100 MHz (with DIV2)
The CPU is running at 720 MHz and DDR at 533 MHz.
Transfer time is calculated by counting elapsed counter ticks in the CP15 performance monitor register.
Step-by-step Instructions
- Open Xilinx SDK.
- Create a Zynq Empty Application Project.
- Import the attached xdmaps_example_no_intr.c (modified from the example provided by the tools to accommodate LQSPI):
http://www.xilinx.com/txpatches/pub/applications/misc/xdmaps_example_no_intr.zip - Be sure that SRC_LQSPI is defined and PROCESSOR_TICKS_TO_US matches your system settings.
Note: I also attached an example tested on 14.2. It does not include the "transfer time" calculation, but it shows how to use the dma to read data from the qspi.
Expected results
Following are the results for 1.0 silicon:
| Read mode at 100 MHZ (DIV2) | Average PL330 transfer time to DDR (MBytes/sec) |
% Bandwidth Vs. theoretical 50 MBytes/sec |
| QUAD OUTPUT - FAST READ (0x6B) | ~ 31 | ~ 62% |
| QUAD IO - FAST READ (0xEB) | ~ 36 | ~ 72% |
Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51779 | Zynq-7000 AP SoC Example Designs | N/A | N/A |
Associated Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 50991 | Zynq-7000 - What devices are supported for configuration? | N/A | N/A |