The 7 Series device family IBERT core has a new feature that can help to evaluate the reliability of a high speed serial link using Xilinx transceivers. The following answer record will provide you with all the information you will need to use this feature in the 7 Series GTX/GTH IBERT cores.
Note: This Answer Record is a part of the Xilinx ChipScope Solution Center (Xilinx Answer 45310). The Xilinx ChipScope Solution Center is available to address all questions related to the ChipScope tool. Whether you are starting a new design with the ChipScope tool or troubleshooting a problem, use the ChipScope Solution Center to guide you to the right information.
The 7 Series IBERT core has a RX margin analysis feature that allows you to see a 2D plot of of your transceiver eye margin. This feature is currently only supported in 7 Series devices. For more information on how to use this feature, please refer to the "Scan Settings" section of the ChipScope User Guide:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_4/chipscope_pro_sw_cores_ug029.pdf
This section will contain all the information needed to use this feature.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45310 | Xilinx ChipScope Solution Center | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 45201 | Xilinx ChipScope Solution Center - IBERT Design Assistant | N/A | N/A |