The VC707 Evaluation Board for the Virtex-7 FPGA User Guide v1.0 (UG885) states on page 37 that U2 (ICS844021I) generates a high-quality, low-jitter, 25 MHz LVDS clock from a 25 MHz crystal (X3).
Is this LVDS clock frequency of 25 MHz correct?
The LVDS clock frequency generated by U2 as stated in UG885 is not correct.
This clock frequency generated by ICS844021I is a high-quality, low-jitter, 125 MHz LVDS clock from a 25 MHz crystal (X3).
This information is going to be corrected in the next revision of the VC707 Evaluation Board for the Virtex-7 FPGA User Guide (UG885).