This example design shows how to program the PL using the following Linux instructions and a raw binary bitstream.
mknod /dev/xdevcfg c 259 0 > /dev/null
cat system.bit.bin > /dev/xdevcfg
Note: An Example Design is an answer record that providestechnical tips to test a specific functionalityon Zynq-7000. Atip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. It isup to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design tofulfill his needs. Limited support is provided by Xilinx on these Example Designs.
| Implementation Details | |||
|---|---|---|---|
| Design Type | PS and PL | ||
| SW Type | Bootgen / Linux | ||
| CPUs | Single CPU | ||
| PS Features | DEVCFG | ||
| PL Cores | -- | ||
| Boards/Tools | ZC702 | ||
| Xilinx Tools Version | EDK 14.1 | ||
| Other details | -- | ||
Open a command line shell (eg, cmd.exe on Windows or simply a shell terminal in Linux) and source the Xilinx tools environment.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 51779 | Zynq-7000 AP SoC Example Designs | N/A | N/A |
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 47002 | Zynq-7000 Debug - How do you program a bitstream using Lauterbach? | N/A | N/A |