This example design uses the FMC1 connector on the ZC702 board to attach the XILINX HW_FMC-105-DEBUG board. The TRACE port gets routed via EMIO to the mictor connector on the FMC-105.
Implementation Details
Design Type: PS and FPGA
SW Type: Standalone
PS Features: TRACE
PL Cores: ---
Boards/Tools: ZC702
Software Tools/Version: EDK 14.1
Other details:
Single core CPU @ 720MHz,FCLK (EMIOTRACECLK ) @ 200MHz, TRACECLK_pin @ 100MHz
Files Provided
Archived XPS project
ps7_init.tcl
Note: A version of the design built using Vivado IP Integrator is also attached.
Simply, create a new Vivado project targeting the ZC702.
Source the .tcl to create the block design.
Add the constraints files.
Generate the output products.
Create the HDL wrapper and generate the bitstream.
In the design, FCLK_CLK0 is used to feed the EMIO port EMIOTRACECLK, and a divided by two version of FCLK_CLK0 is used to feed the external port TRACECLK_pin. This is because ARM defines two separate clocks, TRACECLKIN and TRACECLK, where TRACECLK = TRACECLKIN/2. TRACECLKIN is the input clock to the CoreSight components, and TRACECLK is the output clock that goes to the Lauterbach debugger. On EMIO, the EMIOTRACECLK port is actually TRACECLKIN. You will need to generate your own divide-by-2 version of this clock in the PL, and output it to the TRACECLK_pin.
Make sure that the EMIO TRACECLK is selected as the source clock for trace in the DBG_CLK_CTRL register; bit 6 of 0xF8000164 should be set to 1.
Step-by-step Instructions
The TRACE port is functional.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 50863 | Zynq-7000 AP SoC - Debug | N/A | N/A |