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AR# 46936

IBERT Design Assistant - Advanced Debugging Techniques for IBERT


This answer record discusses some more advanced techniques that can be used for debugging issues you may come across while using IBERT.

Note: This Answer Record is a part of the Xilinx ChipScope Solution Center (Xilinx Answer 45310). The Xilinx ChipScope Solution Center is available to address all questions related to the ChipScope tool. Whether you are starting a new design with the ChipScope tool or troubleshooting a problem, use the ChipScope Solution Center to guide you to the right information.


One of the more common issues when using the IBERT core are when the transceiver does not link or the PLL does not lock. You should first review AR 46136 (Xilinx Answer 46136)which helps troubleshoot issues with the PLL not achieving lock. If that AR does not resolve your issue, the techniques below can help debug the issue further.

The next step involves verifying the settings of the transceiver to ensure they are set correctly. Either of the two methods below will work for this step. Once you have the settings for the IBERT core, you can generate a similar design using the appropriate GT transceiver Wizard (such asVirtex-6 GTX Wizard) and compare the IBERT settings with the settings used in the GT transceiver wizard. Ideally, they should both use similar settings for the same configuration of the transceiver. The appropriate Transceiver user guide can be used asa guide as well to determine what the correct setting should be for any attribute or port of the GT.

Using CORE Generator in Debug Mode

Normally, when you generate an IBERT core, many source files and intermediary files are deleted after the netlist file is created. You can run the CORE Generator tool in debug mode which will prevent the tool from deleting these files. In some cases, it is useful to view the GT wrapper file from the IBERT core so that you can see how the transceiver is configured. Normally, this wrapper file is deleted after netlist creation, but the debug mode will preserve this file.

To run CORE Generator in debug mode and view the IBERT GT wrapper file:

  1. Open up a command line console window and type "coregen -ddd".
  2. Generate the IBERT core just like normal
  3. Once the core has been generated, navigate to the directory where your IBERT core has been generated.
  4. Navigate to the following location with the IBERT core project directory: <IBERT_Core_Name>_debug\_bbx\<chipscope_ibert_<device_name>_gtx_<version_number>
  5. Open the gt_tiles.v file. This is the GT wrapper file for the IBERT core and shows all of the port/attribute assignments for the GT.

Exporting (or importing) all Transceiver settings for the IBERT core

Sometimes, when using IBERT, it is useful to export all current GT settings (attributes and ports) to a file. This can be done in ChipScope Analyzer. Click on the IBERT_V6GTX menu (the exact name will vary depending on your device and transceiver used, ie. IBERT_K7GTX) and click on the "import/export Settings Wizard". This will allow you to export all settings currently set on the transceiver and write this out to a file. Alternatively, you can import settings from a file and use those settings for your transceiver.

If you are still having issues with getting the IBERT core working on your board, please open a webcase at the following link:


Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
45310 Xilinx ChipScope Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46136 IBERT Design Assistant - Debugging PLL locking issues when using IBERT N/A N/A
AR# 46936
Date Created 03/29/2012
Last Updated 03/07/2013
Status Active
Type General Article
  • ChipScope Pro - 13
  • ChipScope Pro - 13.1
  • ChipScope Pro - 13.2
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