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AR# 46955

FPGA - Virtex/7-series - How many DUMMY words are required before the SYNC word? Can I use the Bitgen header for my CVS?

Description

How many DUMMY words are required before the SYNC word? Can I use the Bitgen header for my CVS?

Solution

Our recommended format for both is:

Kintex-7 FPGA

*Miscellaneous header info - SW and Device, Family, Date stamp

11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
00000000000000000000000010111011 // BusWidth Word
00010001001000100000000001000100 // 32/08/16 bits
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
10101010100110010101010101100110 // Sync Word

Virtex-5 FPGA

*Miscellaneous header info - SW and Device, Family, Date stamp

11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
00000000000000000000000010111011 // BusWidth Word
00010001001000100000000001000100 // 32/08/16 bits
11111111111111111111111111111111 // Dummy Word
11111111111111111111111111111111 // Dummy Word
10101010100110010101010101100110 // Sync Word

This will cover all modes and all configuration options - Multiboot, fallback, Power-on, PROG pulse. This includes the bus width detection pattern to determine the bus width for parallel mode. Serial modes will ignore the bus width detection pattern.

Is there any difference between Virtex-5 and Kintex-7 FPGA concerning the number of dummy bytes?
Twodummy words should be sufficient for both for serial modes. In parallel modes we recommend the format above and that is what we test.

Is there any difference between slave serial and master SPI configuration concerning number of dummy bytes?
No, both should work withtwo dummy words before the sync word. A possible exception is where slave serial may send data before the FPGA is ready to receive it. This can occur if there is a slow rise time on INIT and the processor or flash sends data too early.

If you renamed a bin file from Bitgen to .bit, itcan be used to generate an MCS. Another approach to CMS can be to use a .bit file and then script the change of name and add some proprietary header info. This allows customization of the header file, and appending this data to the .bin ensures configuration data integrity.

AR# 46955
Date Created 01/31/2013
Last Updated 01/31/2013
Status Active
Type General Article
Devices
  • Kintex-7
  • Artix-7
  • Virtex-5 FXT
  • More
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Virtex-7
  • Virtex-7 HT
  • Less