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AR# 47012

13.4 Place - ERROR:Place:864 - Incompatible IOBs are locked to the same bank

Description

I am receiving the following error when using LVCMOS33 outputs and LVDS_25 inputs in the same bank:


ERROR:Place:864 - Incompatible IOB's are locked to the same bank 13

Conflicting IO Standards are:

IO Standard 1: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =

INPUT, DRIVE_STR = NR

List of locked IOB's:

clktestn

clktestp

IO Standard 2: Name = LVCMOS33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR =

OUTPUT, DRIVE_STR = 12

List of locked IOB's:

dataout_test

These IO Standards are incompatible due to VCCO mismatch. This mismatch can

be caused by setting DIFF_TERM = TRUE for some IOs locked to the bank

Phase 2.7 Design Feasibility Check (Checksum:266480e0) REAL time: 40 secs

Total REAL time to Placer completion: 40 secs

Total CPU time to Placer completion: 39 secs

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Solution

DIFF_TERM is only available for inputs and can only be used with the appropriate VCCO voltage.

For LVDS_25, VCCO must be 2.5V if DIFF_TERM is used.

To work around the issue, either set the DIFF_TERM of LVDS_25 inputs to FALSE or change VCCO to 2.5V.

LVCMOS33 cannot be used.
AR# 47012
Date Created 03/27/2012
Last Updated 03/11/2015
Status Active
Type General Article
Devices
  • Virtex-7
  • Virtex-7 HT
  • Kintex-7
  • Artix-7