We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47014

Timing - Why are there only "Default ..." constraints but no user constraints in the timing report?


In the timing report, there are no user constraints but only "Default ..." constraints like the following. What is the problem?

Default period analysis for net "cpu_clk"
Default OFFSET IN BEFORE analysis for clock "cpu_clk"
Default OFFSET OUT AFTER analysis for clock "cpu_clk"


This is because the -a option of Timing Analyzer is enabled when generating the timing report. When the -a(advanced analysis) option is used, Timing Analyzer will ignore any user constraints in the UCF and perform automatic timing analysis. This is why there are only "Default..." constraints in the timing report.

This option is only used if you are not supplying any timing constraints (from a PCF) to TRACE. When user wants to generate the timing report based on user constraints, the -a option should not be used.
AR# 47014
Date Created 11/12/2012
Last Updated 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • More
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
  • ISE Design Suite - 14.3
  • ISE Design Suite - 14.4
  • Less