We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47025

MIG Virtex-6 DDR2/DDR3 - x4 RDIMMs have incorrect mapping


MIG generates a linear address scheme for the dq-dqs mapping of x4 RDIMM's, whereas this is non-linear on the memory part.  


This discrepancy was discovered in MIG v3.9 resulting in incorrect x4 RDIMM pin allocation.

Starting with MIG v3.91, a notice was added to the MIG GUI to inform user that MIG does not allocate pins for x4 RDIMM as per the memory part datasheet when x4 RDIMM is selected. 

There are currently no plans to fix this. Only x4 RDIMM's are affected. 

To work around this issue, manually modify the RTL to properly target the module. 

Table 1-92 was added to the Virtex-6 FPGA Memory Interface Solutions User Guide in order to explain the differences in dq-dqs mapping and this table can be used as x4 RDIMM pin map example.
AR# 47025
Date Created 03/28/2012
Last Updated 08/28/2014
Status Active
Type General Article
  • Virtex-6
  • ISE Design Suite
  • MIG Virtex-6 and Spartan-6