After I modify the clock generator parameters, MAP shows errors similar to the following:
ERROR:PhysDesignRules:2449 - The computed value for the VCO operating frequency
of PLL_ADV instance
calculated to be 3000.000000 MHz. This falls above the operating range of the
PLL VCO frequency for this device of 400.000000 - 1080.000000 MHz. Please
adjust either the input frequency CLKINx_PERIOD, multiplication factor
CLKFBOUT_MULT or the division factor DIVCLK_DIVIDE, in order to achieve a VCO
frequency within the rated operating range for this device.
ERROR:Pack:1642 - Errors in physical DRC.