UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47051

MIG Virtex-6 QDRII+ cq_n signals are removed in MAP

Description

When using the MIG QDRII+ SRAM example design, the qdriip_cq_n signals are optimized away in MAP. 

Is this expected behavior?

Solution

These warnings can be safely ignored if the memory interface is running below 250MHz. 


The qdriip_cq_n clock is only used by the phase detector circuitry, but this logic is turned off for memory rates under 250MHz.  


As a result, these signals are not needed in QDRII+ designs running under 250 MHz.

 

 

Revision History:

2/09/2014  Updated for content

 

 

Linked Answer Records

Master Answer Records

AR# 47051
Date Created 03/29/2012
Last Updated 01/07/2015
Status Active
Type General Article
IP
  • MIG Virtex-6 and Spartan-6