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AR# 47066

Artix-7 FPGA - Speed Files Revision History

Description

This answer record contains the Revision History for Artix-7 family speeds files.

Solution

Speeds Files Revision History

1.05 Release: Description and Explanation of Changes - 14.3/2012.3

  • Updated Clocking Modified Blocks (MMCM/PLL) blocks
  • Updated IOB, IOI, IOB blocks
  • Updated RAM and FIFO blocks

(Lower Power) 1.03

  • Updated RAM and FIFO blocks

1.04 Release: Description and Explanation of Changes - 14.2/2012.2

  • Updated Clocking Modified Blocks (MMCM/PLL) blocks
  • Updated IOB blocks
  • Updated IOI, IOB blocks
  • Updated Phaser blocks
  • Updated PCIE blocks
(Lower Power) 1.02
  • Updated IOI, IOB blocks
  • Updated clocking, MMCMand PLL blocks
  • Updated PCIE block

1.03 Release: Description and Explanation of Changes - 14.1/2012.1

  • Updated Clocking Modified Blocks (MMCM/PLL) blocks
  • Updated IOB, IODELAY, IOI blocks
  • Updated SERDES blocks
  • Updated CLB blocks
  • Updated RAM, FIFO blocks

(Lower Power) 1.01

  • Updated CLB , DSP blocks
  • Updated clocking, MMCMand PLL blocks
  • Updated block RAM and FIFO block

1.01 Release: Description and Explanation of Changes - 13.3

  • Updated Clocking
  • Updated CLB
  • Updated Phaser block
  • Updated MMCM
  • Updated block RAM and FIFO block
  • Changed labels to Advanced for 7a8 and 7a15
  • Updated IOB block
  • Updated IODELAY block

1.00 Release: Description and Explanation of Changes - 13.2

  • Updated DSP block
  • Updated block RAM
  • Updated PLL, MMCM, and Clocking
  • Updated Interconnect
AR# 47066
Date Created 03/30/2012
Last Updated 11/05/2012
Status Active
Type General Article
Devices
  • Artix-7