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AR# 47074

Virtex-6 Integrated Block Wrapper v1.7 for PCI Express - Cannot Write to Configuration Space Register of Root Port

Description

I am trying to access the configuration space of the Virtex-6 Integrated Block Wrapper v1.7 for PCI Express.

I am using the provided example design in Root Port configuration.

I have generated the core for VHDL.

After writing a value to a configuration register through the management interface as described in the user guide, it does not work.

Solution

In the 'Xilinx_pcie_2_0_rport_v6.vhd' file in the 'example_design' directory, make the following changes:

From:

signal cfg_wr_rw1c_as_wr_n : std_logic;

To:

signal cfg_wr_rw1c_as_wr_n : std_logic := '1';


Revision History:
04/10/2012 - Initial Release
AR# 47074
Date Created 04/10/2012
Last Updated 03/26/2015
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )