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AR# 47128

Design Advisory for the Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon


This answer record contains information on attribute settings, issues, and work-arounds for Virtex-7 FPGA GTH Transceiver Initial Engineering Sample (ES) Silicon.


1. GTH Transceiver Attribute Updates for Initial Engineering Sample (ES) Silicon

This table shows the GTH attribute updates required for reliable operation of the Initial ES silicon as noted under "ISE 14.1."

The following attribute updates marked as "ISE 14.1" can be generated natively when using v2.2 of the 7 series FPGA Transceiver Wizard in the ISE 14.2/Vivado 2012.2 or later tools.

GTH Attributes

ISE 13.4 default ISE 14.1 DFE LPM
RX_CM_TRIM 4'b0100 4'b1010(1)
BIAS_CFG 64'h0 64'h0000040000001050(2)

ES_HORZ_OFFSET 12'h0 12'h000
ADAPT_CFG0 20'h0 20'h00C10
PMA_RSV2 32'h0 32'h1C00000A
PMA_RSV4 15'h0 15'h0008
RX_BIAS_CFG 24'h0 24'h0C0010
RX_DFE_AGC_CFG1 3'h2 3'h4 3'h4 3'h2
RX_DFE_GAIN_CFG 23'h181C0F 23'h0000C0 23'h0020C0 23'h0020C0
RX_DFE_H2_CFG 12'h1E0 12'h000
RX_DFE_H3_CFG 12'h1E0 12'h040
RX_DFE_H4_CFG 11'h0F0 11'h0E0
RX_DFE_H5_CFG 11'h0F0 11'h0E0
RX_DFE_H6_CFG 11'h0 11'h020(2)
RX_DFE_H7_CFG 11'h0 11'h020(2)
RX_DFE_KL_CFG 33'h0000003F0 33'h000000310
RX_DFE_KL_LPM_KH_CFG0 2'h1 2'h1 2'h2 2'h1
RX_DFE_KL_LPM_KL_CFG0 2'h1 2'h2 2'h2 2'h1
RX_DFE_KL_LPM_KL_CFG2 4'h3 4'h2
RX_DFE_LPM_CFG 16'h0 16'h0080
RX_DFE_ST_CFG 54'h0 54'h00_E100_000C_003F
RX_DFE_UT_CFG 17'h03F00 17'h03800

RX_DFE_VP_CFG 17'h03F00 17'h3AA3
RX_OS_CFG 13'h03F0 13'h0080
RXLPM_HF_CFG 14'h03F0 14'h0200
RXLPM_LF_CFG 18'h003F0 18'h09000
PMA_RSV 32'h0 32'h00000080
CFOK_CFG 42'h0000000000 42'h248_0004_0E80(3)
CFOK_CFG2 6'b000000 6'b100000

CFOK_CFG3 6'b000000 6'b100000
RXOSCALRESET_TIMEOUT 5'b01100 5'b00000
RXOSINTCFG 4'b0000 4'b0110
RXOSINTEN 1'b0 1'b1

All Protocols except PCIe Gen1 & PCIe Gen2

PCIe Gen1 &Gen2
CPLL_CFG 29'h00B007D8 24'h00BC07DC 24'h00A407CC
PCS_RSVD_ATTR[8] 1'b0(1) 1'b0(1)


1.Default PCS_RSVD_ATTR[8] = 1'b0means OOB powered down. OOB circuitry must be powered on (1'b1) for applications such as PCI Express, SATA/SAS. For designs not using OOB,RXELECIDLEMODE[1:0] must be set to 2'b11and RXBUF_RESET_ON_EIDLE must be set to FALSE.

ISE version PPM variation Divider, Line Rate RXCDR_CFG(4) RXCDR_LOCK_CFG (5)
ISE 13.4 default
83'h0_0011_07FE_4060_0108_0000 6'b001001
ISE14.1 0,+/-200PPM RXOUT_DIV=1,>=8.5 Gb/s 83'h0_0011_07FE_4060_0104_1010 6'b010101
ISE14.1 +/- 700PPM

RXOUT_DIV=1,>=8.5 Gb/s

83'h0_0011_07FE_4060_2104_1010 6'b010101
ISE14.1 0,+/-200PPM RXOUT_DIV=1,< 8.5 Gb/s 83'h0_0011_07FE_4060_0104_1010 6'b010101
ISE14.1 0, +/- 200PPM RXOUT_DIV=2, 1.6 - 6.55 Gb/s 83'h0_0001_07FE_2060_0110_1010 6'b010101
ISE14.1 +/- 700PPM,1250PPM RXOUT_DIV=2, 1.6 - 6.55 Gb/s 83'h0_0001_07FE_2060_2110_1010 6'b010101
ISE 14.1 0, +/- 200PPM RXOUT_DIV=4, 0.8 - 3.275 Gb/s 83'h0_0001_07FE_1060_0110_1010 6'b010101
ISE 14.1 +/- 700PPM,1250PPM RXOUT_DIV=4, 0.8 - 3.275 Gb/s 83'h0_0001_07FE_1060_2110_1010 6'b010101
ISE 14.1 0, +/- 200PPM RXOUT_DIV=8, 0.4 - 1.6375 Gb/s 83'h0_0001_07FE_0860_0110_1010 6'b010101
ISE 14.1 +/- 700PPM,1250PPM RXOUT_DIV=8, 0.4 - 1.6375 Gb/s 83'h0_0001_07FE_0860_2110_1010 6'b010101
Attribute ISE 13.4 ISE14.1:VCO Rate = 6.6 Gb/s to 13.1 Gb/s (QPLL/CPLL) ISE 14.1:VCO Rate = 1.6 Gb/s to 6.6 Gb/s (CPLL)
RXPI_CFG1 2'b0 2'b11 2'b0
RXPI_CFG2 2'b0 2'b11 2'b0
RXPI_CFG3 2'b0 2'b11 2'b11
RXPI_CFG4 1'b0 1'b0 1'b1
RXPI_CFG5 1'b0 1'b0 1'b1
RXPI_CFG6 3'b100 3'b100 3'b001
Attribute ISE13.4 default
Line rates <= 11.3 Gb/s Line rates > 11.3and <= 12 Gb/s Line rates >12and <= 13.1 Gb/s
QPLL_CFG 27'h0480181 27'h04801C7 27'h04801C7 27'h0480187
QPLL_LOCK_CFG 16'h21E8 16'h05E8 16'h01E8 16'h01E8
QPLL_CLKOUT_CFG 4'b0000 4'b1111 4'b1111 4'b1111

1. Programmable, set to 800 mV.
2. Must be set manually through version ISE version 14.4
3. For simulation speed-up, CFOK_CFG needs to be set a different value. Please see (Xilinx Answer 47318) for details.
4. The RXCDR_CFG settings are preliminary and are under characterization. The final settings will be added when available.
5. The RXCDRLOCK port is not supported. The port RXCDRLOCK is only a coarse indicator of CDR lock and it is recommended to verify the incoming data as well.

GTH Ports

Port Value
ISE 13.4 default ISE 14.1 DFE LPM
RXDFEAGCHOLD 1'b0 1'b0 1'b1 after convergence(1)
RXDFEAGCTRL 5'h00 5'h10
1'b0 1'b1 after convergence(1)
RXLPMHFHOLD 1'b0 1'b0 1'b1 after convergence(2)
RXLPMLFHOLD 1'b0 1'b0 1'b1 after convergence(2)
RXDFEXYDEN 1'b0 1'b1(3)

1. In DFE mode, the RXDFEAGCHOLD and RXDFELFHOLD should be asserted after training (waiting time of "TDLOCK" = 1.0207E+08 bits in DFE mode) to freeze the AGC adapt value.
2. In LPM mode, the RXLPMHFHOLD and RXLPMLFHOLD should be asserted after training (waiting time of "TDLOCK" to be determined for LPM mode, but the same value above in DFE mode can be used) to freeze the LPM adapt value.
3.RXDFEXYDEN must be set manually to 1'b1 in v2.1 or earlier of the wizardin ISE 14.1/Vivado 2012.1; set to 1'b1 by default in v2.2 or later of wizard in ISE 14.2/Vivado 2012.2 or later.

2. Use Modes

2.1. GTH Transceiver Eye Scan:
RX_DATA_WIDTH of 20 and 40 are not supported by Eye Scan. For RX_DATA_WIDTHof 16, 32, or 64, the use mode described in (Xilinx Answer 47425) must be followed to enable proper operation of Eye Scan.

2.2. GTHE2_COMMON/BIAS_CFG Use Model Change:

BIAS_CFG is an attribute of the GTHE2_COMMON module and its value depends on the PLL driving the channel, and the correct QPLL settings are covered in the attribute table. However, for the correct BIAS_CFG to propagate through, the following use mode must be followed. Otherwise, BIAS_CFG will be set incorrectly in the software model to 64'h0000000000000000.

To use the correct BIAS_CFG value when using 7 series GTH Transceiver Wizard v2.1 or earlier, perform the following steps:

  1. Instantiate GTH2_COMMON in every Quad used in the design even if the QPLL is not used in that Quad.
  2. Define the correct value of BIAS_CFGin the wrapper or UCF.

Note: After setting BIAS_CFG as above, the minimum connections required so that the tools do not optimize the GTHE2_COMMON block away are as follows:

1. GTHE2_COMMON port GTREFCLK0 should be connected to the incoming reference clock.
2. GTHE2_COMMON port QPLLOUTCLK should be connected to GTHE2_CHANNEL port QPLLCLK (all the used channels on the quad).
3. GTHE2_COMMON port QPLLREFCLKSEL should be 3'b001.

The GTHE2_COMMONinstantiations should be done in the gtwizard_v2_1.v file for Verilog or gtwizard_v2_1.vhd for VHDL (gtwizard_v2_1 is the default name that will be replaced with the name that the user gives to the design onpage 1 of the wizard). The GTHE2_COMMON instantiation can be obtained from a wizard example design that uses QPLL (sample"gt_wizard_v2_2.v" and "gt_wizard_v2_2.vhd" files are attached to show an example where two GTHE2_COMMON's are instantiated).

The GTHE2_COMMON module is automatically instantiated when using the 7-Series GTH Transceiver Wizard v2.2 or later in ISE 14.2/Vivado 2012.2 or later.

2.3. Termination Use Modes:

For the different RX termination use modes, refer to (Xilinx Answer 50146).

2.4. ACJTAG Use Mode:

For details on the ACJTAG use mode, refer to (Xilinx Answer 52431).

3. Issues

3.1. Incorrect GTH Resistor Calibration:

The GTH resistor calibration circuitry on the Initial ES silicon devices may not calibrate to the expected value. For additional information, please refer to (Xilinx Answer 50147).

NOTE: After further investigation and analysis, it has been determined that there are no issues with the GTH resistor calibration circuitry . This work-around in (Xilinx Answer 50147) is not required to be implemented and should be removed. This issue will be removed from this section in afuture update to this design advisory.

4. GTH Initial ES Silicon Errata Items

4.1. GTH Transceiver Link Margin Reduction:

There can be a reduction in link margin, in the form of increased transmitter output jitter and reduced receiver input jitter tolerance, when multiple GTH channels are used. For additional information, please refer to (Xilinx Answer 50063).

4.2. RXOUTCLK Port:

The GTH transceiver RXOUTCLK port, when configured to use the RXOUTCLKPCS or the RXOUTCLKPMA path, can exhibit a phase jump of up to two UI of the line rate. This issue applies when the GTH line rate is above 8.5 Gb/s. For additional information, please refer to (Xilinx Answer 50064).

Revision History
02/08/2013 - AddedPCS_RSVD_ATTR[8] and note
01/23/2013 - Added QPLL_CLKOUT_CFG and update CPLL_CFG for PCIe Gen 1 & Gen 2
01/14/2013 - Updated the values for Bias_cfgandqpll_cfg.
10/16/2012 - Added the ACJTAG use mode.
08/09/2012 - Updated the GTHE2_COMMON/BIAS_CFG section to specify which file to update with the new instantiations and also addedan example. Also added some references to ISE 14.2/Vivado 2012.2 in general.
07/27/2012 - Updated the Incorrect GTH Resistor Calibration section that there is no issue and no work-around is required.
07/12/2012 - Updated the QPLL_CFG and QPLL_LOCK_CFG values for different line rates and updated the answer record for GTH Transceiver Link Margin Reduction.
06/28/2012 - Updated PMA_RSV2, RX_BIAS_CFG, RXDFEXYDEN values in the attributes and ports section.
05/24/2012 - Added GTHE2_COMMON use mode change, termination use modes, the Initial ES errata items section, and modified the resistor calibration section.
05/14/2012 - Added the incorrect resistor calibration section and the updated BIAS_CFG value to the table.
05/02/2012 - Initial release


Associated Attachments

Name File Size File Type
gtwizard_v2_2.v 25 KB V
gtwizard_v2_2.vhd 33 KB VHD

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
50063 7 Series FPGA GTH Transceiver Initial ES CES9937 Silicon - Link Margin Reduction N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42944 Design Advisory Master Answer Record for Virtex-7 FPGA N/A N/A
AR# 47128
Date Created 05/02/2012
Last Updated 03/08/2013
Status Active
Type Design Advisory
  • Virtex-7
  • Virtex-7 HT