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AR# 47247

MIG 7 Series DDR2/DDR3 - multi-cycle XDC constraints incorrectly set when I/O Power Reduction is disabled

Description

Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 45195)

When the "I/O Power Reduction" option is turned ON in the MIG GUI, new I/O primitives are used in the RTL code which require multi-cycle path constraints.
When the "I/O Power Reduction" option is turned OFF, these multi-cycle constraints are not required.

However the multi-cycle constraints are still being generated for the XDC constraint file used in PlanAhead and Vivado and will cause the following Critical Warnings:

CRITICAL WARNING: [PlanAhead-1387] set_multicycle_path: specified list for option 'from' is an empty list. The constraint will not be applied. Please check to make sure that this is intended. [/project_name/mig_7series_v1_5/example_design/par/proj1.srcs/constrs_1/imports/par/example_top.xdc:305]

Solution

These Critical Warnings can be safely ignored as these constraints are only required when "I/O Power Reduction" is enabled.

The following constraints can also be removed from the XDC constraint file to remove the warning message:

set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
-setup 6
set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
-to [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
-hold 5


There is no issue with the constraints generated for the UCF as these multi-cycle constraints are correctly removed.
AR# 47247
Date Created 04/23/2012
Last Updated 08/13/2014
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG 7 Series