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AR# 47259 MIG 7 Series DDR2/DDR3 - VHDL designs fail during simulation using ISIM

Description

Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

When MIG 7 Series DDR2/DDR3 VHDL designs are simulated with ISIM the following error occurs:

ERROR:HDLCompiler:845 - "../../user_design/rtl/phy/ddr_phy_top.vhd" Line 1646: Type of aggregate cannot be determined without context ; 8 visible types match here.

Solution

All MIG VHDL designs are failing simulating when using ISIM as a result of ISIM not supporting the following piece of code:

po_counter_load_val => (others => '0'),

Instead of having "others" in port mapping to work around the issue. the user needs to connect to a vector that is assigned a value of all zeros. For example, the above piece of code could be changed as follows:

po_counter_load_val => others_zeros, //Where others_zeros is assigned with values of all zeros.

This issue only affects the ISIM simulator as ModelSim has no problems handling this construct.

Actions

AR# 47259
Date Created 04/23/2012
Last Updated 04/23/2012
Status Active
Type
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
IP
  • MIG 7 Series
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