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AR# 47285

13.4 ISE / Spartan-6 - PAR reports a local clock for cascading BUFGs.

Description

In Spartan-6, when a BUFG has some BUFGMUX loads, the clock is reported as a local. 


Is this report correct?

WARNING:ParHelpers:79 -
The following Clock signals are not routed on the dedicated
global clock routing resources. This will usually result in
longer delays and higher skew for the clock load pins. This could
be the result of incorrect clock placement, more than 8 clocks
feeding logic in a single quadrant of the device, or incorrect
logic partitioning into the quadrant(s). Check the timing report
to verify the delay and skew for this net
Net Name: pllclk50m_out

+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_selout | BUFGMUX_X3Y13| No | 2 | 0.000 | 1.664 |
+---------------------+--------------+------+------+------------+-------------+
| pllclk100m_out | BUFGMUX_X2Y1| No | 1 | 0.000 | 1.083 |
+---------------------+--------------+------+------+------------+-------------+
| pllclk50m_out | Local| | 2 | 0.000 | 1.084 |
+---------------------+--------------+------+------+------------+-------------+

Solution

The message is correct.

There are no dedicated routing resources for cascaded BUFGs in Spartan-6.

The only routing option for the upper BUFG sites to BUFG loads is to use local resources.
AR# 47285
Date Created 04/17/2012
Last Updated 03/23/2015
Status Active
Type General Article
Devices
  • FPGA Device Families