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AR# 47316 7 Series Integrated Block for PCI Express v1.3 - Enabling OOB Clock Mode

Description


Version Found: v1.3
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

Xilinx recommends enabling the OOB clocking mode option in the integrated block wrapper. This enables a separate 62.5 MHz clock input on the CLKSRSVD0 input pin of the MGT that is used to clock the OOB circuitry inside the MGT instead of the input reference clock. This clock needs to be a low frequency clock.

If the reference clock frequency used is 250 MHz, this will be needed, otherwise the link will not be stable due to the MGTs incorrectly signaling electrical idle to the block. However, Xilinx recommends enabling this mode for all frequencies and will be the default starting with the v1.5 release.

Solution


To work around this issue, please follow these steps:

Verilog Mode

1. Edit the xilinx_pcie_2_1_ep_7x.v file in the example_design directory to add the following wire. This connection is missing which causes the clock to not connect from the external clocking module instantiated in this file to the underlying wrapper files.

wire PIPE_OOBCLK_IN;

2. In the generated core's source directory, edit the file < generated core name >_gt_top.v and enable the PCIE_OOBCLK_MODE parameter. Find the instantiation of the pipe_wrapper_i module (around line 336) and change the PCIE_OOBCLK_MODE parameter to 1.

VHDL Mode

If the generated core selected VHDL for the wrapper, the connection is already present in the top level file. The only change needed is in the < generated core name >_gt_top.vhd file. In the file, find the instantiation of the pipe_wrapper_i file (around line 602) and change the PCIE_OOBCLK_MODE generic from 0 to 1.

Important Note

In the v1.4 or v1.3 release, if the PCIE_OOBCLK_MODE is enabled, then the core will not link train during simulation. This is only a simulation problem and hardware works fine. For simulation, change the parameter back to 0 and regardless of the reference clock speed, there will be no issue during simulation if not using the extra OOB clock.

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/01/2012 - Initial release

Actions

AR# 47316
Date Created 05/01/2012
Last Updated 05/01/2012
Status Active
Type
IP
  • 7 Series Integrated Block for PCI Express ( PCIe )
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