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AR# 47318

7 Series FPGA GTH Transceivers - Long simulation run times


This answer record discusses the long simulation run times for 7 Series GTH Transceivers and the work-around.


The current software model for GTHE2 makes the simulation runtime slower compared to the GTXE2 software model, specifically on the RXCDRLOCK assertion after the transceiver is reset/initialized.

For ISE tool versions prior to 14.4, please use the following work-around to make the simulation run faster:

CFOK_CFG[8] = 1'b1

Current recommended setting for GTH:

CFOK_CFG = 42'h248_0004_0E80 for hardware

In simulation, please change the setting of this attribute to speed up simulation:

CFOK_CFG = 42'h248_0004_0F80

This runtime issue is scheduled to be fixed in the ISE 14.4 design tools. After this is fixed in 14.4, the above work-around is no longer necessary.

AR# 47318
Date Created 04/25/2012
Last Updated 03/04/2013
Status Active
Type General Article
  • Virtex-7