UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47350

MIG 7 Series DDR2/DDR3 - Synplicity fails to compile VHDL designs

Description

Version Found: v1.5
Version Resolved and other Known Issues: See(Xilinx Answer 45195).

Synplicity fails to compile the MIG 7 Series DDR2/DDR3 VHDL designs.

The following error message is received:

@E: CD629 :"./mig_7series_v1_5/user_design/rtl/phy/ddr_phy_top.vhd":625:5:625:6|Failed to evaluate generic ctl_bank

Solution

This is an issue with the Synplify Pro VHDL compiler and is scheduled to be fixed in a future version of Synplify.

There is no workaround for Synplify, so XST must be used as a workaround if the VHDL design is required.
AR# 47350
Date Created 04/23/2012
Last Updated 08/26/2014
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Artix-7
  • Virtex-7
IP
  • MIG 7 Series