We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47364

Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Example Design Simulation Timeout using Modelsim 10.1a


When using Mentor Graphics ModelSim 10.1a to simulate configurations of the Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper with the 1000BASE-X PCS/PMA physical interface and the 16-bit client interface, simulations may timeout with an error message such as: "ERROR: Simulation Running Forever" or "ERROR - Testbench timed out".


To work around this simulator issue, use Mentor Graphics ModelSim 6.6d, or a supported simulator from a different vendor.
AR# 47364
Date Created 04/20/2012
Last Updated 04/20/2012
Status Active
Type General Article
  • Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper