UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47400

Soft Error Mitigation Controller - Vivado 2012.1 period constraint rounded up to next whole nanosecond

Description


Version Found: v3.2
Version Resolved and other Known Issues: see (Xilinx Answer 44541).

Timing constraints in the Vivado 2012.1 produced XDC file are rounded to the nearest nanosecond.

Solution


Timing constraints in the XDC file should be reviewed for accuracy. For example, for a desired clock frequency of 70 MHz, adjust the create_clock clock period constraint from:
create_clock -name clk -period 15 [get_ports clk]

to:
create_clock -name clk -period 14.286 [get_ports clk]

NOTE: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History
05/08/2012 - Initial release
AR# 47400
Date Created 04/23/2012
Last Updated 05/02/2012
Status Active
Type Known Issues
IP
  • Soft Error Mitigation