AR# 47406 Zynq-7000 Example Design - CPU throughput to access an AXI Slave using Master AXI GP
Description
This example design allocates 4K of block RAM attached to the M_AXI_GP0 and monitored by the ChipScope tool. Thesoftware then treats the memory as a "shareable device" or "strongly-ordered," and a ChipScope shot provides the distance between two consecutives BVALID signals on the AXI port for THROUGHPUT.
Note: An Example Design is an answer record that providestechnical tips to test a specific functionalityon Zynq-7000. Atip can be a snippet of code, a snapshot, a diagram or a full design implemented with a specific version of the Xilinx tools. It isup to the user to "update" these tips to future Xilinx tools releases and to "modify" the Example Design tofulfill his needs. Limited support is provided by Xilinx on these Example Designs.
| Implementation Details | |||
|---|---|---|---|
| Design Type | PS and PL | ||
| SW Type | Standalone | ||
| CPUs | Single CPU @ 720MHz | ||
| PS Features | MMU | ||
| PL Cores | BRAM, CHIPSCOPE | ||
| Boards/Tools | ZC702 | ||
| Xilinx Tools Version | EDK 14.1 | ||
| Other details | FCLK @ 150MHz | ||
| Address Map | |||
| Base Address | Size | Bus Interface | |
| BRAM | 0x41200000 | 4K | S_AXI |
| Files Provided | |||
| bram_archive.zip | Archived XPS project. | ||
| code.c | Snippet of code. | ||
Block Diagram | |||
 | |||
Solution
Step-by-Step Instructions
- Import the archived design into XPS and export to SDK.
- In SDK, create a Hello World example.
- Modify the Hello World example to include the snippet of C code.
- Program the PL using the BITSTREAM generated by XPS.
- Set up ChipScope to trigger on the BVALID signal.
- Run the application.
- Measure the throughput as the time between two consecutive BVALID signals on the AXI Master Interface.
Expected Results
Throughput | |||
Type |
FCLK Cycles |
CPU Cycles |
Time (nS) |
| Strongly-ordered | |||
| Shareable device | 3 |
14 |
20 |
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