We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 47423

MIG 7 Series RLDRAM II - Missing PHASER_IN constraint causes Placer error


Version Found: v1.5
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

MIG 7 Series RLDRAM II designs may fail during placement in Vivado with the following ERROR and Critical Warning:

ERROR: [Place-370] An unconstrained Phaser instance has been found. Phaser instances and their associated IO logic must be LOC constrained to a legal site locations for placement to succeed. Check to see whether all core constraints were properly used or manually add LOC constraints for the following instance(s).

Unconstrained Phaser instance(s):
Inst 'PHASER_IN_inst.phaser_in'

CRITICAL WARNING: [EDIF-96] Could not resolve non-primitive black box cell 'qdr_rld_byte_group_io_parameterized1' defined in file '/proj/mig_7series_v1_5/user_design/rtl/phy/qdr_rld_byte_group_io.v' instantiated as 'qdr_rld_byte_group_io'.


This issue exists for x18 parts with data widths of 18 or 36 when data is placed on byte groups T1 and T2, and T0 and T3 are not selected for data.

In this configuration, MIG allocates Write Clocks (DK/DK#) into the T0 or T3 byte group and the MIG RTL is coding a PHASER_IN for this byte group.

This PHASER_IN constraint is missing from the XDC constraint file and causes placement errors in the Vivado flow only.

To work around the issue, the PHASER_IN constraint must be manually placed into the XDC constraint file.
AR# 47423
Date 10/20/2014
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • MIG 7 Series
Page Bookmarked