Design Assistant

Xilinx Vivado HLS Solution Center - Design Assistant

This answer record covers reference designs and general design tips for Vivado HLS.

NOTE: This answer record is part of the Xilinx Vivado HLS Analysis Solution Center (Xilinx Answer 47428). The Xilinx Vivado HLS Solution Center is available to address all questions related to Vivado HLS.

Free video trainings are available at the Xilinx Training site:
Vivado High-Level Synthesis Training

Directive Behaviors
(Xilinx Answer 42565) Vivado HLS - Can the internal FIFO depth be forced with set_directive_interface -depth option?
(Xilinx Answer 44786) Vivado HLS - Sharing internal AP_STREAMs and its scope

Tool Implementation Behaviors
(Xilinx Answer 43172) Vivado HLS - What is the difference between ap_(u)int and sc_big(u)_int regarding shift left operation?

Top FAQs
(Xilinx Answer 43472) Vivado HLS - How does Vivado HLS name the output HDL files?
(Xilinx Answer 46243) Vivado HLS - How do you run RTL simulation with standalone RTL simulator?
(Xilinx Answer 45856) Vivado HLS - Does the Vivado HLS tool support designs that processes variable sized images?

Design Debug
(Xilinx Answer 43934) Vivado HLS - How can I get information on Critical Paths in my design?

Methodology

• Verification
• Free online video training
• csim_design: Starting with 2012.3 Vivado HLS, csim_design command can be run to compile and run C simulation.
• Self-checking test bench
• Refer to Vivado HLS user guide "Coding Style Guide" section for more information.
• Use bit-accurate data types if the range is known
• Simulate design after any update to C and debug in C.
• Enables fast and accurate simulation in C.
• Refer to Vivado HLS user guide "C++ Arbitrary Precision Types" section for more information.
• Use directives to allow exploration
• Create different solutions from the same source with different directives.
• Embed directives into the source as pragma before releasing the code as IP.
• Pipelining
• Pipeline whenever possible to take advantage of hardware concurrency.
• Variable loop boundaries does not allow pipeline.
• Loops must be unrolled.
• Avoid unrolling large loops completely to avoid extensive resource usage
• The more objects, the greater the search space, run time, and memory.
• Automatic RTL verification

Coding

• Remove Mallocs
• Use fixed sized arrays instead.
• Refer to Vivado HLS user guide for more information and sample code.
• Use the stream class for streaming interfaces designs
• Use the hls::stream<> class for streaming data.
• Allows streaming to be modeled in C.
• Synthesized to streaming interface and FIFO.
• Refer to Vivado HLS user guide for more information.
• Do not partition large arrays with variable indexing
• Partitioning large array with variable indexing will result in the array being broken into registers and numerous LUTs.
• If index is not variable, the address will be resolved and reduce resource consumption.
• Use array indices instead of pointers
• Pointing to fixed sized resource will allow the logic to synthesize to RAM.
• Inline vs. Preserve hierarchy
• Inline allows greater optimization.
• Inline flattens hierarchy and creates more objects which results in higher runtime and memory.
• Use data packing to merge different fields in a struct
• Ensures common signals will share common control logic.
• Will result in better grouping and higher QoR.

For all Vivado HLS design assistant answer records, use the "Search" box on the upper left corner of the Xilinx Support Page to search for "Vivado HLS design assistant".
A filter can be applied to answer records specific to a version.

Answer Number	Answer Title	Version Found	Version Resolved
44786	AutoESL - Sharing internal AP_STREAMs and its scope	N/A	N/A
44265	AutoESL - Simulation lasting extended hours	N/A	N/A
43934	Vivado HLS - How can I get information on Critical Paths in my design?	N/A	N/A
43472	Vivado HLS - How does Vivado HLS name the output HDL files?	N/A	N/A
43172	Vivado HLS - What is the difference between ap_(u)int and sc_big(u)_int regarding shift left operation?	N/A	N/A
42565	Vivado HLS - Can the internal FIFO depth be forced with set_directive_interface -depth option?	N/A	N/A
46635	AutoESL - Simple System Generator and AutoESL Integration Costas Loop Example	N/A	N/A
46243	Vivado HLS - How do you run RTL simulation with a standalone RTL simulator?	N/A	N/A
46037	AutoESL- ATAN LUT Function Example	N/A	N/A
45810	AutoESL - Integration of AutoESL Design with AP_FIFO and AXI_Stream Interface into System Generator using Blackbox Flow	N/A	N/A
45798	AutoESL - Simple System Generator and AutoESL Integration FFT Example	N/A	N/A
45518	Vivado HLS - Checklist for DSP48s mappings	N/A	N/A
50496	Vivado HLS - When a directive is applied, does it propagate down the levels in the code?	N/A	N/A
50929	AutoESL - Zynq EPP Design Example with AXI-DMA Core for Data Transfer	N/A	N/A
46358	Vivado HLS - RTL Port and signal width implementation.	N/A	N/A

Documentation

Xilinx Vivado HLS Solution Center - Documentation

This answer record covers available user guides, library guides, and tutorials for the AutoESL .

NOTE: This answer record is part of the Xilinx Vivado HLS Solution Center (Xilinx Answer 47428). The Xilinx Vivado HLS Solution Center is available to address all questions related to Vivado HLS.

AutoESL 2011.3 - A user guide is provided with the tool installation.
AutoESL 2011.4 - A user guide is provided with the tool installation.
AutoESL 2011.4.2 - A user guide is provided with the tool installation.
AutoESL 2012.1 - A user guide, Coreand Operator Guide, Tutorial: Introduction, Tutorial: Integrating with EDK, and Coding Style Guide are provided with the tool installation.
Vivado HLS - Documentation is available online and can be accessed through the Xilinx Documentation Navigator application, or go to: www.xilinx.com -> Documentation (at the top of the page) -> click the Design Tools tab -> Vivado Design Suite section.

Design Advisories

Design Advisory Master Answer Record for Xilinx Vivado HLS Tool

Design Advisory Answer Records are created for issues that are important to designs currently in progress and can be selected to be included in the Xilinx Alert Notification System.

Note: This Answer Record is part of the Xilinx Vivado HLS Solution Center (Xilinx Answer 47428). The Xilinx Vivado HLS Solution Center is available to address all questions related to Vivado HLS tool.

There are no design advisories for Vivado HLS.

Top Issues

Xilinx Vivado HLS Solution Center - Top Issues

This answer record covers current known issues related to the Vivado HLS tool.

This answer record is part of the Xilinx Vivado HLS Solution Center; see (Xilinx Answer 47428). The Xilinx Vivado HLS Solution Center is available to address all questions related to Vivado HLS tools.

Top Issues

(Xilinx Answer 43271) AutoESL - RTL Implementation results in "@E [IMPL-4] 'autoimpl' failed: 'xtclsh' cannot be found. Please check your PATH variable."
(Xilinx Answer 51042) Vivado HLS - RTL export result in "@E [IMPL-28] Failed to generate IP." or "@E [IMPL-4] 'xtclsh' cannot be found. Please check your PATH variable."
(Xilinx Answer 50152) Vivado HLS- Java 2 Platform Standard Edition binary has stopped working
(Xilinx Answer 50501) Vivado HLS - Running Verilog or VHDL simulation with ModelSim results in errors

Vivado HLS Known Issues

For Vivado HLS known issues, use the "Search" box on the upper left corner of the Xilinx Support Page.
A filter can be applied to sort out known issues specific to a version. There are also issues that might affect multiple tool versions.

Answer Number	Answer Title	Version Found	Version Resolved
43271	AutoESL - RTL Implementation Results in "@E [IMPL-4] 'autoimpl' failed: 'xtclsh' cannot be found. Please check your PATH variable."	N/A	N/A
50152	Vivado HLS - Java 2 Platform Standard Edition binary has stopped working	N/A	N/A
50495	AutoESL - Synthesis reports error "@E [SYNCHK-74] Recursive functions are not supported: recursion found in the following functions 'ap_fixed_base --> 'ap_fixed_base'"	N/A	N/A
50501	Vivado HLS - Running Verilog or VHDL simuation with ModelSim results in errors	N/A	N/A
51019	2012.2 Vivado HLS - Known Issues	N/A	N/A
51042	Vivado HLS - RTL export results in "@E [IMPL-28] Failed to generate IP" or "@E [IMPL-4] 'xtclsh' cannot be found. Please check your PATH variable."	N/A	N/A

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