Free video trainings are available at the Xilinx Training site:
Vivado High-Level Synthesis Training

Directive Behaviors
(Xilinx Answer 42565) Vivado HLS - Can the internal FIFO depth be forced with set_directive_interface -depth option?
(Xilinx Answer 44786) Vivado HLS - Sharing internal AP_STREAMs and its scope

Tool Implementation Behaviors
(Xilinx Answer 43172) Vivado HLS - What is the difference between ap_(u)int and sc_big(u)_int regarding shift left operation?

Top FAQs
(Xilinx Answer 43472) Vivado HLS - How does Vivado HLS name the output HDL files?
(Xilinx Answer 46243) Vivado HLS - How do you run RTL simulation with standalone RTL simulator?
(Xilinx Answer 45856) Vivado HLS - Does the Vivado HLS tool support designs that processes variable sized images?

Design Debug
(Xilinx Answer 43934) Vivado HLS - How can I get information on Critical Paths in my design?

Methodology

• Verification
• Free online video training
• csim_design: Starting with 2012.3 Vivado HLS, csim_design command can be run to compile and run C simulation.
• Self-checking test bench
• Refer to Vivado HLS user guide "Coding Style Guide" section for more information.
• Use bit-accurate data types if the range is known
• Simulate design after any update to C and debug in C.
• Enables fast and accurate simulation in C.
• Refer to Vivado HLS user guide "C++ Arbitrary Precision Types" section for more information.
• Use directives to allow exploration
• Create different solutions from the same source with different directives.
• Embed directives into the source as pragma before releasing the code as IP.
• Pipelining
• Pipeline whenever possible to take advantage of hardware concurrency.
• Variable loop boundaries does not allow pipeline.
• Loops must be unrolled.
• Avoid unrolling large loops completely to avoid extensive resource usage
• The more objects, the greater the search space, run time, and memory.
• Automatic RTL verification

Coding

• Remove Mallocs
• Use fixed sized arrays instead.
• Refer to Vivado HLS user guide for more information and sample code.
• Use the stream class for streaming interfaces designs
• Use the hls::stream<> class for streaming data.
• Allows streaming to be modeled in C.
• Synthesized to streaming interface and FIFO.
• Refer to Vivado HLS user guide for more information.
• Do not partition large arrays with variable indexing
• Partitioning large array with variable indexing will result in the array being broken into registers and numerous LUTs.
• If index is not variable, the address will be resolved and reduce resource consumption.
• Use array indices instead of pointers
• Pointing to fixed sized resource will allow the logic to synthesize to RAM.
• Inline vs. Preserve hierarchy
• Inline allows greater optimization.
• Inline flattens hierarchy and creates more objects which results in higher runtime and memory.
• Use data packing to merge different fields in a struct
• Ensures common signals will share common control logic.
• Will result in better grouping and higher QoR.

For all Vivado HLS design assistant answer records, use the "Search" box on the upper left corner of the Xilinx Support Page to search for "Vivado HLS design assistant".
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