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AR# 47448

LogiCORE IP Serial RapidIO Gen2 v1.3 - Tvalid behavior in back-to-back transaction

Description

When receiving packets continuously in back-to-back from the SRIO core, two types of "Tvalid" behavior are observed:

1. Tvalid de-asserts just after Tlast

2. It keeps asserting high level.

What causes these different behaviors?

Solution

Both behaviors are valid.

Characteristics of Tvalid:


  • You are likely to see b2b (back to back) packets, especially when a stream of packets are all destined for the same user interface,
  • If every alternating packet goes to a different destination, there will always be a silent cycle after tlast (across all interfaces).
  • An RX buffer that is running lean will tend to put dead cycles between packets.
     

The core is going to send back-to-back packets whenever it can. 

In summary, the core can make a decision on whether to send back-to-back packets or put a dead cycle between the packets.

AR# 47448
Date Created 04/25/2012
Last Updated 10/13/2014
Status Active
Type General Article
IP
  • Serial RapidIO