The Vivado Synthesis tool does not currently support this mixed-language support feature of accessing a Verilog module from a VHDL entity using the work library as mentioned above. Vivado Synthesis will result in the following error message in this situation:
"ERROR: [Synth-493] no such design unit 'gate_inst' [box.vhd:19]"
The Vivado Synthesis development team will revisit these types of mixed language issues and fix them if there are repeated requests from the customer in the future.
To work around this issue, declare the Verilog module as a VHDL component declaration within the VHDL entity, then instantiate the Verilog module as a regular VHDL instantiation. Vivado Synthesis supports this work-around and the synthesis completes successfully.
Following is an example for the work-around which gets synthesized successfully by the Vivado Synthesis tool:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity box is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : out STD_LOGIC);
end box;
architecture Behavioral of box is
COMPONENT gate PORT (
A : in std_logic;
B : in std_logic;
C : out std_logic);
END COMPONENT;
begin
GATE_INST: gate
port map (
A => A,
B => B,
C => C);
end Behavioral;
In the above example, instance gate is a simple Verilog module representing an AND gate.