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AR# 47490

Vivado Timing - Clocking with two clock inputs results in timing violation in single clock domain

Description

The following violation is seen for MMCM/PLL output clock, if two clock inputs are set in clocking wizard.

Slack (VIOLATED) : -1.871ns
Source: counters[2].counter_reg[2][15]/Q
(rising edge-triggered cell FDCE clocked by clknetwork/clkout1_1 {rise@0.000ns fall@2.780ns period=6.666ns})
Destination: counters[2].counter_reg[2][15]/D
(rising edge-triggered cell FDCE clocked by clknetwork/clkout1 {rise@0.000ns fall@4.170ns period=10.000ns})
Path Group: clknetwork/clkout1
Path Type: Max at Slow Process Corner
Requirement: 0.002ns
Data Path Delay: 1.396ns (logic 0.364ns (26.080%) route 1.032ns (73.920%))
Logic Levels: 1 (CARRY4=1)
Clock Path Skew: -0.409ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.836ns
Source Clock Delay (SCD): 4.245ns
Clock Pessimism Removal (CPR): 0.000ns
Clock Uncertainty: -0.068ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.116ns
Phase Error (PE): 0.000ns

How can I resolve the violation?

Solution

In XDC, all clocks are related by default. You must tell the engine which ones are not related, even the ones propagating on the same tree. Use set_clock_groups -physically_exclusive in such cases.

set_clock_groups -physically_exclusive -group [get_clocks -include_generated_clocks -of [get_pins clknetwork/plle2_adv_inst/CLKIN1]] -group [get_clocks -include_generated_clocks -of [get_pins clknetwork/plle2_adv_inst/CLKIN2]]

This instructs the tool that CLKIN1 and CLKIN2, and their derived clocks, cannot be used at the same time.

AR# 47490
Date Created 05/01/2012
Last Updated 08/07/2013
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2012.1
  • Vivado Design Suite - 2012.3
  • Vivado Design Suite - 2012.4
  • More
  • Vivado Design Suite - 2013.1
  • Vivado Design Suite - 2013.2
  • Less