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AR# 47511 Zynq-7000 AP SoC, SPI - In Master Mode on MIO, the SPI Controller Resets Itself when the SS0 Signal Asserts

Description

When the SPI controller is configured as a master, the SS0 signal is an output. The unused input signal from the MIO/EMIO multiplexer must remain deasserted. When using an MIO interface, route the SS0 controller signals to the EMIO interface and assign the EMIO SS0 input signal to net_vcc (this may not be the default setting).

Solution

Impact: Minor, it affects usage of SS 0 in master mode.
Work-arounds: Please see Article Details section.
Configurations
Affected: 		Systems using the SPI controller via the MIO interface.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record

When interfacing via MIO or EMIO:

1. Do not enable the SPI SS0 signal on any of the MIO pins.

2. Configure the EMIO SPI SS0 port signal in the MHS file so its an output and the SS input is tied to net_vcc:

  • PORT processing_system7_0_SPI0_SS_O_pin = processing_system7_0_SPI0_SS_O, DIR = O
  • PORT SPI0_SS_O = processing_system7_0_SPI0_SS_O
  • PORT SPI0_SS_I = net_vcc
Note: the ISE 14.1 default settings connect the EMIO SS0 output to the input and causes the controller to reset when the controller asserts SS 0.

The SS 0 signal cannot be used via MIO, but may be used via EMIO. It is theoretically possible to use SS 0 via EMIO and the remainder of the SPI signals via MIO, but that is not recommended because of timing concerns and its not supported by the design tools.

Actions

AR# 47511
Date Created 05/23/2012
Last Updated 02/11/2013
Status Active
Type Design Advisory
Devices
  • Zynq-7000
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