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AR# 47512

Zynq-7000 AP SoC, DDR - LPDDR2 Dynamic Clock-Stop Restarts Too Soon


The user can program the LPDDR2 controller to stop the DRAM clock when there are no memory transactions to perform and restart the clock when a memory request is received. The controller correctly stops the clock whenever the transaction queue is empty, but when the clock is restarted, the controller quickly issues a DRAM transaction. It does not recognize the tXP timing parameter value.

Either do not use the LPDDR2 clock-stop feature or have software ensure that the enable/disable of the clock-stop is only done when there is no DRAM activity.


Impact: Minor, see Work-around Details.
Work-arounds: Do not use the stop-clock feature, or
Manually program the stop clock feature when DRAM is inactive
Systems using the PS DDR controller in LPDDR2 mode
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record

When clock_phy_stop is enabled for LPDDR2, the controller correctly stops the clock to DRAM whenever the transaction queue is empty. Before restarting the clock, it is supposed to wait tXP plus two clock cycles (about five clock cycles), but it does not. LPDDR2 clocks can be restarted too soon if the transaction queue gets a new transaction before the required delay period.

Work-around Details: If clock-stop feature is desired, software must stop the clock by asserting the reg_ddrc_clock_stop_en bit. Software must take care to only do this when it is certain there is no traffic on the host interface. Software must wait tXP plus two clock cycles before re-enabling the clock.

AR# 47512
Date Created 05/23/2012
Last Updated 11/12/2012
Status Active
Type Design Advisory
  • Zynq-7000