Under certain circumstances with the cache disabled, the DDR Controller does not respond properly to an Exclusive Store (STREX) instruction executed by a CPU. This can be avoided by executing the STREX instruction only in cacheable memory space with the cache enabled.
Impact: Minor, it is very rare that the system locks-up.
Work-around: If the masters that require the exclusive operations are limited to the ARM cores, by making the region that requires exclusive operations cacheable and having the L1 caches enabled, the problem can be prevented. Furthermore, if one of the masters happens to be in the PL, an Exclusive monitor can be implemented in the PL and the accesses from the ARM CPUs and the fabric master are routed to that monitor.
Configurations Affected: Systems that issue Exclusive operations to the DDR memory controller.
Device Revision(s) Affected: Refer to (Xilinx Answer 47916) - Zynq-7000 Design Advisory Master Answer Record.
DDRC does not generate a proper response when it executes the STREX instruction under certain circumstances. The following sequence of exclusive operations demonstrates a scenario under which the STREX instruction gets mishandled.